The present invention relates to a bus circuit, and more particularly, to a bus circuit for signal transmission/reception by a plurality of circuit devices via a common bus signal line.
As an example of a conventional bus circuit of this type, Japanese Patent Application Laid-Open No. Sho 61-58317 discloses two conventional bus circuits.
Referring to FIGS. 5(A) through 5(C), a first conventional bus circuit 600 has a feedback circuit 610 and bus input/output circuits 671 and 672. The bus circuit 600 is a static-type bus circuit. The feedback circuit 610 comprises a hysteresis circuit 612 which receives a bus signal, a buffer 613 which receives an output from the hysteresis circuit 612, and a transfer gate transistor 614 which receives an output from the buffer 613. The transfer gate transistor 614 is in an off state during the first-half cycle of a data transfer period, then it is in an on state during the last-half cycle of the data transfer period for transmitting the output from the buffer 613 to a bus signal line 601.
If the circuit is designed such that the level V1 is lower than a low-level judgment level V.sub.L of the hysteresis circuit 612, a signal, which is obtained through the hysteresis circuit 612 and the buffer 613, accelerates the discharge potential on the bus signal line 601. When the transfer data signal is at a high level, high-speed operation is similarly attained by designing the circuit such that a rising voltage V2 of the bus signal line 601 in the first-half cycle of the data transfer cycle is higher than a high-level judgment level V.sub.H. In the first conventional bus circuit, since a feedback circuit is additionally connected to the bus signal line 601, the hardware in the bus circuit and the amount of load on the bus signal line increase.
In FIGS. 6(a), 6(b) and 6(c), a bus circuit 700 includes a precharge transistor 702, a feedback circuit 710 and bus input/output circuits 771 and 772. The second conventional bus circuit 700 is a dynamic (precharge) type bus circuit. The feedback circuit 710 comprises a comparator 712 which receives a bus signal, a 2-input NOR gate 715, to which an output from the comparator 712 and a precharge signal T.sub.PC are inputted, and a pull-down transistor 713 which inputs an output from the 2-input NOR gate 715 as a gate input for pulling down a bus signal line 701. The feedback circuit 710 is connected to the bus signal line 701.
The bus signal line 701 is charged when the precharge transistor 702 is turned on by the precharge signal T.sub.PC. When low level data is transferred in the data transfer cycle, the bus signal line 701 is discharged by discharge transistors 734 and 730 in the bus input/output circuit 771. When the level of the bus signal line 701 becomes lower than a low-level judgment level V.sub.L of the comparator 712 as shown in FIG. 6(c), the pull-down transistor 713 is turned on by the output of the NOR gate 15. While the feedback circuit 710 accelerates the discharge from the bus signal line 701, since the feedback circuit 710 is additionally connected to the bus signal line 701, the amount of hardware of the bus circuit and the load on the bus signal line also increase.
A third conventional bus circuit is disclosed in Japanese Patent Application Laid-Open No. Hei 2-135817.
Referring to FIG. 7, a third conventional bus circuit 800 has a bus signal line 801, a p-channel transistor 802, a driver (bus output circuit) 890, a receiver (bus input circuit) 880 and includes at least one discharge circuit (auxiliary circuit) 810a.
The p-channel precharge transistor 802 is turned on by the precharge signal T.sub.PC and charges the signal line 801 at a high level. Thereafter, when the bus selection signal T.sub.OUT is at a high level and the data signal D.sub.in is at a high level, the n-channel transistors 834 and 830 in the driver 890 turns on, and discharge from the bus signal line 801 is started through the driver 890. When the potential of the bus signal line 801 begins to decrease, the gate potential of a p-channel transistor 812 in the discharge circuit (auxiliary circuit) 810a decreases. Accordingly, the p-channel transistor 812 turns on, and a high potential is supplied from the power source line 803a to a gate of the n-channel transistor 813. As a result, the n-channel transistor 813 turns on, and a current flows from the bus signal line 801 to a ground line 800a, promoting the discharge from the bus signal line 801. In the third conventional bus circuit, however, since the discharge circuit (auxiliary circuit) 810a is additionally connected to the bus signal line 801, the amount of hardware of the bus circuit and the load on the bus signal line also increase.
A fourth conventional bus circuit is disclosed in Japanese Patent Application Laid-Open No. Hei 3-74722.
In FIG. 8, a fourth conventional bus circuit 900 includes a bus signal line 901 and a precharge transistor 902 which charges the bus signal line 901. As the precharge transistor 902 is an n-channel transistor, the bus signal line 901 turns on at an intermediate level. A bus input circuit 980 input a signal from the bus signal line 901 via a n-channel transistor 929. After the bus signal line 901 is charged by a precharge transistor 902, the bus control circuit 979 turns the precharge transistor 902 off by a signal on the precharge signal line 909. At the same time, the bus output control means 999 turns a bus output transistor 930 on, and drives the bus signal line 901 to a low level. As the bus signal line was at the intermediate level at the time of precharge, the bus signal line 901 can be driven in a shorter period. The n-channel transistor 919 is turned on by the precharge signal. As the level of the bus signal line 901 approaches the low level, the output of the inverter 912 becomes high. The n-channel transistor 913 is turned on, and the level of the bus signal line 901 immediately becomes low. However, since the auxiliary circuit is additionally connected to the bus signal line 901, the amount of hardware of the bus circuit and the load on the bus signal line also increase.
In the above described conventional bus circuits, a problem is created because the amount of hardware of the bus circuit increases due to addition of the auxiliary circuit to the bus signal line. Therefore, high integration of the bus circuit is prevented.
Moreover, since the auxiliary circuit is connected to the bus signal line, the amount of load on the bus signal line increases, which increases transmission delay time on the bus signal line. As a result, high speed operation is prevented. Further, the operation cycle period of the bus circuit cannot be reduced, and the transmission efficiency is lowered.